Disadvantage of usb3.0

Ø The first batch of Motherboard’s which will be shipping with USB 3.0 will be costly but with the technology getting older price too will go down

Ø USB 3.0 is incompatible with USB 1.1

Ø USB 3.0 only supports a maximum cable length of 3 meters compared to 5 meters of USB 2.0

Ø Another major disadvantage of USB 3.0 is that mobile phones and other gadgets which will use the Micro-B USB 3.0 connector will have a width of 12.25mm while the Micro-B USB 2.0 Connector is only 6.86mm wide.

Ø Currently there are no OS available in the market which supports USB 3.0 and even the upcoming version of Windows i.e. Windows 7 will not support USB 3.0 though Microsoft may add support for it later on via Windows Update.

As you can see, currently USB 3.0 has more disadvantages than advantages but with time the disadvantages of USB 3.0 will reduce significantly which will help in making USB 3.0 mainstream.

Advantages OF usb3.0

Ø Faster Data Transfer Speed

Ø Ø Lower Power Consumption by the USB Devices

3.Protocol Layer

The protocol layer defines the “end-to-end” communications rules between a host and device .

The SuperSpeed protocol provides for application data information exchanges between a host and a device endpoint. This communications relationship is called a pipe. It is a host-directed protocol, which means the host determines when application data is transferred between the host and device. SuperSpeed is not a polled protocol, as a device is able to asynchronously request service from the host on behalf of a particular endpoint.

All protocol layer communications are accomplished via the exchange of packets. Packets are

sequences of data bytes with specific control sequences which serve as delimiters managed by the link layer. Host transmitted protocol packets are routed through intervening hubs directly to a peripheral device. They do not traverse bus paths that are not part of the direct path between the host and the target peripheral device. A peripheral device expects it has been targeted by any protocol layer packet it receives. Device transmitted protocol packets simply flow upstream through hubs to the host.

Packet headers are the building block of the protocol layer. They are fixed size packets with type and subtype field encodings for specific purposes. A small record within a packet header is utilized by the link layer (port-to-port) to manage the flow of the packet from port to port. Packet headers are delivered through the link layer (port-to-port) reliably. The remaining fields are utilized by the end-to-end protocol.

Application data is transmitted within data packet payloads. Data packet payloads are preceded (in the protocol) by a specifically encoded data packet headers. Data packet payloads are not delivered reliably through the link layer (however, the accompanying data packet headers are delivered reliably). The protocol layer supports reliable delivery of data packets via explicit acknowledgement (header) packets and retransmission of lost or corrupt data. Not all data information exchanges utilize data acknowledgements.

Data may be transmitted in bursts of back-to-back sequences of data packets (depending on the scheduling by the host). The protocol allows efficient bus utilization by concurrently transmitting and receiving over the link. For example, a transmitter (host or device) can burst multiple packets of data back-to-back while the receiver can transmit data acknowledgements without interrupting the burst of data packets. The number of data packets in a specific burst is scheduled by the host. Furthermore, a host may simultaneously schedule multiple OUT bursts to be active at the same time as an IN burst.

The protocol provides flow control support for some transfer types. A device-initiated flow control is signaled by a device via a defined protocol packet. A host-initiated flow control event is realized via the host schedule (host will simply not schedule information flows for a pipe unless it has data or buffering available). On reception of a flow control event, the host will remove the pipe from its schedule. Resumption of scheduling information flows for a pipe may be initiated by the host or device. A device endpoint will notify a host of its readiness (to source or sink data) via an asynchronously transmitted “ready” packet. On reception of the “ready” notification, the host will add the pipe to its schedule, assuming that it still has data or buffering available. Independent information streams can be explicitly delineated and multiplexed on the bulk transfer type. This means through a single pipe instance, more than one data stream can be tagged by the source and identified by the sink. The protocol provides for the device to direct which data stream is active on the pipe.

Devices may asynchronously transmit notifications to the host. These notifications are used to convey a change in the device or function state. A host transmits a special packet header to the bus that includes the host’s timestamp. The value in this packet is used to keep devices (that need to) in synchronization with the host. In contrast to other packet types, the timestamp packet is forwarded down all paths not in a low power state. The timestamp packet transmission is scheduled by the host at a specification determined period.

2.Link Layer

A SuperSpeed link is a logical and physical connection of two ports. The connected ports are called link partners. A port has a physical part and a logical part. The link layer defines the logical portion of a port and the communications between link partners.

The logical portion of a port has:

>> State machines for managing its end of the physical connection. These include physical layer initialization and event management, i.e., connect, removal, and power management.

>> State machines and buffering for managing information exchanges with the link partner. It implements protocols for flow control, reliable delivery (port to port) of packet headers, and link power management.

>> Buffering for data and protocol layer information elements.

The logical portion of a port also:

Ø Provides correct framing of sequences of bytes into packets during transmission; e.g., insertion of packet delimiters

Ø Detects received packets, including packet delimiters and error checks of received header packets (for reliable delivery).

Ø Provides an appropriate interface to the protocol layer for pass-through of protocol-layer packet information exchanges.

The physical layer provides the logical port an interface through which it is able to:

Ø Manage the state of its PHY (i.e., its end of the physical connection), including power management and events (connection, removal, and wake).

Ø Transmit and receive byte streams, with additional signals that qualify the byte stream as control sequences or data. The physical layer includes discrete transmit and receive physical links, therefore, a port is able to simultaneously transmit and receive control and data information.

The protocol between link partners uses specific encoded control sequences. Note that control sequences are encoded to be tolerant to a single bit error. Control sequences are used for port-to- port command protocol, framing of packet data (packet delimiters), etc. There is a link-partner protocol for power management that uses packet headers.

1.Physical layer

The physical layer defines the PHY portion of a port and the physical connection between a downstream facing port (on a host or hub) and the upstream facing port on a device. The SuperSpeed physical connection is comprised of two differential data pairs, one transmit path and one receive path (see Figure). The nominal signaling data rate is 5 Gbps. The electrical aspects of each path are characterized as a transmitter, channel, and receiver; these

collectively represent a unidirectional differential link. Each differential link is AC-coupled with capacitors located on the transmitter side of the differential link. The channel includes the electrical characteristics of the cables and connectors.

At an electrical level, each differential link is initialized by enabling its receiver termination. The transmitter is responsible for detecting the far end receiver termination as an indication of a bus connection and informing the link layer so the connect status can be factored into link operation and management.

When receiver termination is present but no signaling is occurring on the differential link, it is

considered to be in the electrical idle state. When in this state, low frequency periodic signaling (LFPS) is used to signal initialization and power management information. The LFPS is relatively simple to generate and detect and uses very little power.

Each PHY has its own clock domain with Spread Spectrum Clocking (SSC) modulation. The

USB 3.0 cable does not include a reference clock so the clock domains on each end of the physical connection are not explicitly connected. Bit-level timing synchronization relies on the local receiver aligning its bit recovery clock to the remote transmitter’s clock by phase-locking to the signal transitions in the received bit stream.
The receiver needs enough transitions to reliably recover clock and data from the bit stream. To assure that adequate transitions occur in the bit stream independent of the data content being transmitted, the transmitter encodes data and control characters into symbols using an 8b/10b code. Control symbols are used to achieve byte alignment and are used for framing data and managing the link. Special characteristics make control symbols uniquely identifiable from data symbols. A number of techniques are employed to improve channel performance. For example, to avoid overdriving and improve eye margin at the receiver, transmitter de-emphasis may be applied when multiple bits of the same polarity are sent. Also, equalization may be used in the receiver with the characteristics of the equalization profile being established adaptively as part of link training. Signal (timing, jitter tolerance, etc.) and electrical (DC characteristics, channel capacitance, etc.) performance of SuperSpeed links are defined with compliance requirements specified in terms of transmit and receive signaling eyes. The physical layer receives 8-bit data from the link layer and scrambles the data to reduce EMI emissions. It then encodes the scrambled 8-bit data into 10-bit symbols for transmission over the physical connection. The resultant data are sent at a rate that includes spread spectrum to further lower the EMI emissions. The bit stream is recovered from the differential link by the receiver, assembled into 10-bit symbols, decoded and descrambled, producing 8-bit data that are then sent to the link layer for further processing

SuperSpeed (USB 3.0) Architecture

The SuperSpeed bus is a layered communications architecture that is comprised of following elements:

Ø SuperSpeed Interconnect. The superspeed interconnect is the manner in which devices are connected to and communicate with the host over the superspeed bus.This includes the topology of devices connected to bus, the communication layers, the relationships between them and how they interact to accomplish information exchanges between the host and devices.

Ø Devices. SuperSpeed devices are sources or sinks of information exchange. They implement the required device –end, SuperSpeed communications layers to accomplish information exchange between a driver on host and logical function on device.

Ø Host. A SuperSpeed host is a source or sinks of information. It implements the required host-end,SuperSpeed communication layers to accomplish information exchanges over the bus. It owns the SuperSpeed data activity schedule and management of the SuperSpeed bus and all devices connected to it.

see in figure The rows (device or host , protocol , link , physical ) realize the communication layers of the SuperSpeed interconnect.

There are total three layers:

1) Physical layer

2) Link layer

3) Protocol layer

Cable Construction

See in below figure a USB 3.0 cable cross-section. There are three groups of wires:

TP 1) UTP pair,

2) Shielded Differential Pair(SDP, twisted or twinax signal pairs),

3) Power and ground wires.

The UTP is intended to transmit the USB 2.0 signaling while the SDPs are for SuperSpeed, the shield is needed for the SuperSpeed differential pairs for signal integrity and EMI performance.Each SDP is attached with a drain wire, which is eventually connected to the system ground through the GND_DRAIN pin(s) in the connector.

A metal braid is required to enclose all the wires in the USB 3.0 cable. The braid is to be terminated to the plug metal shells, close to 360° as possible, to contain EMI.

Cable Wire Assignments :

Wire Number	Signal Name	Description	Color
1	PWR	Power	Red
2	UTP_D-	Unshielded twist pair,negative	White
3	UTP_D+	Unshielded twist pair,positive	Green
4	GND_PWRrt	Ground for power return	Black
5	SDP1-	Shielded differential pair 1, negative	Blue
6	SDP1+	Shielded differential pair 1, positive	Yellow
7	SDP1_Drain	Drain wire for SDP1	-----------
8	SDP2-	Shielded differential pair 2, negative	Purple
9	SDP2+	Shielded differential pair 2, positive	Orange
10	SDP_Drain	Drain wire for SDP2	-----------
Braid	Shield	Cable external braid to be 360° Terminated on to plug metal shell	-----------

USB 3.0 Cable

USB 3.0 cables have eight primary conductors: Three twisted signal pairs for USB data paths and a power pair. (See in figure) the basic signal arrangement for the USB 3.0 cable. In addition to the twisted signal pair for USB 2.0 data path, two twisted signal pairs are used to provied the SuperSpeed data path ,one for the transmit path and one for the receive path.

USB 3.0 receptacles (both upstream and downstream) are backward compatible with USB 2.0 connector plugs. USB 3.0 cables and plugs are not intended to be compatible with USB 2.0 upstream receptacles. As an aid to users , USB3.0 mandates standard coloring for plastic portions of USB 3.0 plugs and receptacles.

Electrical (insertion loss, return loss, crosstalk, etc.) performance for USB 3.0 is defined with regard to raw cables, mated connectors, and mated cable assemblies ,with compliance requirements using industry test specification established for the latter two categories. Similarly, mechanical (insertion/extraction forces, durability , etc.) and environmental (temperature life, mixed flowing gas, etc.) requirements are defined and compliance established via recognized industry test specification.

USB 3.0 Bus Architecture

USB 3.0 is physical SuperSpeed bus combination in parallel with a physical USB 2.0 bus(see in figure).It has similar architecture components as USB 2.0.

The USB 3.0 interconnect is the manner in which USB 3.0 and USB 2.0 devices connect to and communicate with the USB 3.0 host. The USB 3.0 interconnect inherits core architecture elements from USB 2.0,although several are augmented to accommodate the dual bus architecture.

The baseline strucutral topology is same as USB 2.0. It consists of a tiered star topology with a single host at tier 1 and hubs at lower tires to provide bus connectivity to devices.

The USB 3.0 connection model accommodates backwards and forward compatibility for connecting USB 3.0 or USB 2.0 devices into a USB 3.0 bus. similarly, USB 3.0 devices can be attached to a USB 2.0 bus. The mechanical and electrical backward/forwards compatibility for USB 3.0is accomplished via a composite cable and associated connector assembles that from the dual-bus architecture.USB 3.0 devices accomplish backward compatibility by including both SuperSpeed and non-SuperSpeed bus interface which are essentially parallel buses that may be active simultaneously.

The USB 3.0 connection model allows for the discovery and configuration of USB devices at the highest signaling speed supported by the device, the highest signaling speed supported by all hubs between the host and device,and the current host capability and configuration.

USB 3.0 hubs are a specific class of USB device whose purpose is to provide additional connection points to the bus beyond those provided by the host. In this specification, non-hub devices are referred to as peripheral devices in order to differentiate them from hub devices. In addition , in USB 2.0 the term “function ” was sometimes used interchangeably with device. In this specificaton a function is a logical entity within a device.

History USB 3.0

USB 3.0

The USB 3.0 specification was released on November 12, 2008 by the USB 3.0 Promoter Group. Its maximum transfer rate is up to 10 times faster than the USB 2.0 release. It is also known as SuperSpeed USB.

Now we go on details of usb 3.0.

History USB 2.0

USB 2.0

The USB 2.0 specification was released in April 2000 and was standardized by the USB-IF (USB Implementers Forum) at the end of 2001. It is also known as HighSpeed USB. Hewlett-Packard, Intel, Lucent Technologies (now Alcatel-Lucent following its merger with Alcatel in 2006), Microsoft, NEC, and Philips jointly led the initiative to develop a higher data transfer rate than the 1.0 specification (480 Mbit/s vs 12 Mbit/s).

History

USB 1.0

The USB 1.0 specification was introduced in 1996. It is also known as FullSpeed USB. USB was created by a core group of companies that consisted of Compaq, Digital, IBM, Intel, Northern Telecom, and Microsoft. It was intended to replace the multitude of connectors at the back of PCs, as well as to simplify software configuration of communication devices. The original USB 1.0 specification had a data transfer rate of 12 Mbit/s. It is intended primarily to save cost in low-bandwidth human interface devices (HID) such as keyboards, mice, and joysticks.

What is USB?

USB (Universal Serial Bus) is a way of setting up communication between a computer and peripheral devices. USB is intended to replace many varieties of serial and parallel ports. USB can connect computer peripherals such as mice, keyboards, PDAs, gamepads and joysticks, scanners, digital cameras, printers, personal media players, flash drives, and external hard drives. For many of those devices, USB has become the standard connection method. USB was designed for personal computers, but it has become commonplace on other devices such as PDAs and video game consoles, and as a power cord between a device and an AC adapter plugged into a wall plug for charging. As of 2008, there are about 2 billion USB devices sold per year, and about 6 billion total sold to date.
The design of USB is standardized by the USB Implementers Forum (USB-IF), an industry standards body incorporating leading companies from the computer and electronics industries. Notable members have included Agere (now merged with LSI Corporation), Apple Inc., Hewlett-Packard, Intel, Microsoft and NEC.
Provides three Advantages
1) Port expansion
2) Performance
3) Standard connection method